Cell Modeling and Verification Engineer - New College Grad 2026
Core
Develop behavioral models and verification for custom mixed-signal design cells used across NVIDIA products.
Role type
Cell Modeling and Verification Engineer
Builds
Custom mixed-signal design cells for NVIDIA SoCs and GPUs
Domain
Semiconductor / ASIC Design
Required skills
Verilog HDL, SystemVerilog, RTL simulation, waveform debug, Python scripting, Perl scripting, digital design concepts, logic design
Preferred skills
Digital design experience, Verilog simulation experience, cross-functional collaboration
Technologies
Verilog, SystemVerilog, Perl, Python, PLL, high-speed interconnects
Responsibilities
Develop behavioral models and verification for custom mixed-signal design cells; Use Verilog, SystemVerilog, Perl, or Python to model, verify, emulate/prototype mixed-signal designs; Collaborate with cross-function teams on library build, cell integration, ASIC verification, and DFT simulation; Document, implement, and deliver fully verified and high-performance RTL.
Seniority
Entry-level (New College Grad 2026)
