Cell Modeling and Verification Engineer - New College Grad 2026
Core
Develop behavioral models and verification for custom mixed-signal design cells used in NVIDIA's ASIC products and GPUs.
Role type
Cell Modeling and Verification Engineer (New College Grad)
Builds
Custom mixed-signal design cells for NVIDIA SoCs and GPUs
Domain
Semiconductor / ASIC Design / Digital & Mixed-Signal
Deliverable
production ML models | product features
Required skills
Verilog HDL, SystemVerilog, RTL simulation, waveform debug, Python scripting, Perl scripting, digital design concepts, logic design
Preferred skills
Digital design experience, Verilog simulation experience
Technologies
Verilog, SystemVerilog, Perl, Python, PLL, high-speed interconnects
Responsibilities
Develop behavioral models and verification for custom mixed-signal design cells; Use Verilog/SystemVerilog/Perl/Python to model, verify, and emulate mixed-signal designs; Collaborate on library build, cell integration, ASIC verification, and DFT simulation; Document and deliver fully verified high-performance RTL.
Seniority
Entry-level (New College Grad 2026)