Design / DFT Director (NVE Engineering)
Core
Lead global DFT strategy, architecture, and execution for advanced NAND Flash products, integrating AI/ML and data analytics to optimize testability, diagnostics, and silicon learning.
Role type
Senior leadership IC (Director) in semiconductor DFT
Builds
Scalable test architectures, AI-enabled DFT workflows, and high-performing global engineering teams
Domain
Semiconductor (NAND Flash memory) + AI/ML
Deliverable
production ML models
Required skills
DFT architecture, NAND design expertise, AI/ML strategy, team leadership, simulation-to-silicon correlation, Python/C++ scripting
Preferred skills
Non-volatile memory test algorithms, embedded self-test/diagnostics, production test optimization, distributed team management, EDA/IP partner collaboration
Technologies
Python, C/C++, AI/ML frameworks, EDA tools
Responsibilities
Define global DFT vision and technical roadmap; own DFT architecture and coverage closure; partner with Design/Test/Manufacturing to optimize yield and time-to-market; drive AI/ML adoption for test-pattern optimization and yield prediction; build and mentor a high-performing global DFT organization
Seniority
Director, strategic leadership with hands-on technical depth