Principal Design Engineer
Core
Lead architecture and design of internal datapath blocks (page buffer-to-IO buses, wave pipelines, FIFOs, sense amps) for NAND memory products, integrating AI into design, timing closure, and verification workflows.
Role type
Principal Design Engineer (IC/Analog-Digital Mixed-Signal)
Builds
High-performance NAND memory chips with embedded AI-driven design flows
Domain
Semiconductor / Memory / IC Design
Deliverable
production ML models
Required skills
NAND datapath architecture, flop-to-flop and wave-pipelined timing closure, dataline sensing design, array repair and redundancy, AI for RTL generation and timing analysis, semi-custom methodology, physical co-design
Preferred skills
NAND/DRAM/SRAM periphery experience, memory repair and yield optimization, timing-adjustment techniques (DLL/DCC), AI agent and LLM pipeline development, CMOS device physics and low-power techniques
Technologies
SPICE, SDC, STA, Python, AI/LLM frameworks, custom cell libraries
Responsibilities
Define and verify datapath blocks to meet bandwidth and power targets; architect and close timing paths across PVT conditions; design sense amps and redundancy logic; lead the transition to semi-custom design flows; champion daily AI adoption for automation and analysis; mentor engineers and define technical direction
Seniority
Principal, hands-on IC design with strategic leadership