Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group
Core
Own and evolve timing-critical circuitry between the NAND array and page buffer to deliver robust, scalable datapath solutions.
Role type
Principal Design Engineer (Non-Volatile Memory)
Builds
NAND datapath circuits, array redundancy circuits, wave pipeline/pulse-based datapath architecture, and data line sensing circuits.
Domain
Semiconductor / Non-Volatile Memory (NAND Flash)
Required skills
CMOS analog/mixed-signal circuit design, device physics fundamentals, high-speed datapath timing analysis, layout parasitics management, SPICE/Fast-SPICE simulation, Monte Carlo analysis, root-cause analysis for yield issues, design review leadership, mentorship
Preferred skills
NAND/DRAM datapath design experience, wave-pipelining/self-timed/pulse-latched techniques, redundancy/repair architecture in dense arrays, DRAM interface experience (DDR4/5, LPDDR5/6, HBM3/3E/4), CMOS device reliability knowledge
Technologies
SPICE, Fast-SPICE, Monte Carlo, PVT analysis, CMOS
Responsibilities
Define scalable datapath architecture supporting multi-plane and high-parallelism operation; Define and analyze clock/data timing schemes for long interconnects; Drive layout-aware circuit design with parasitic-aware sizing; Perform SPICE/Fast-SPICE simulations across PVT, aging, and variability; Lead design reviews and mentor engineers; Communicate specifications for major block interfaces
Seniority
Principal, hands-on IC design with technical direction