ENGINEER, DESIGN
Core
Drive physical implementation of advanced NAND Flash digital designs from synthesized netlist through tape-out, owning block- and subsystem-level implementation.
Role type
Senior Digital Implementation / Auto Place & Route Engineer
Builds
Physical GDSII layouts for complex digital blocks and subsystems
Domain
Semiconductor / Memory / Digital Physical Design
Required skills
Digital physical design, automated place-and-route flows, floorplanning, clock tree synthesis, timing closure, physical sign-off (DRC/LVS), scripting (Tcl/Python/Perl), industry-standard EDA tools (Cadence/Synopsys)
Preferred skills
NAND Flash design, mixed-signal SoC integration, advanced technology nodes, hierarchical implementation, low-power techniques
Technologies
Cadence Innovus/Tempus, Synopsys Fusion Compiler/IC Compiler II/PrimeTime, Tcl, Python, Perl
Responsibilities
Own end-to-end RTL-to-GDSII physical implementation; Develop and optimize floorplans, power distribution, placement, and routing; Drive timing closure across multi-mode scenarios; Perform physical sign-off checks (DRC, LVS, IR-drop, etc.); Collaborate with RTL, verification, and analog teams; Develop scripts to automate implementation flows
Seniority
Senior, hands-on IC
