Principal ASIC Design Engineer
Core
Principal ASIC Design Engineer owning RTL design, micro-architecture, and timing closure for high-speed interface digital blocks in a mixed-signal chip.
Role type
Principal ASIC Design Engineer (Digital)
Builds
High-speed interface ASICs (PHY solutions) for memory and storage applications
Domain
Semiconductor / Memory & Storage / High-Speed Interfaces
Deliverable
production ML models | product features
Required skills
SystemVerilog RTL design, Logic Synthesis, Static Timing Analysis, CDC analysis, RTL simulation and debug, Mixed-signal design interface, Technical documentation
Preferred skills
Place-and-route, Physical verification, Mixed-signal/PHY implementation, High-speed PHY architectures, DFT methodologies, Formal property verification
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold, Cadence Innovus, Mentor Calibre
Responsibilities
Define and document block-level architecture specifications and interface control documents; Execute logic synthesis and drive optimization toward PPA targets; Develop and maintain SDC constraints and execute static timing analysis; Serve as primary digital interface to layout and implementation teams; Self-verify RTL through block-level simulation and waveform debug; Collaborate on verification plans and support lab bring-up
Seniority
Principal, hands-on IC
