Principal Layout Designer
Core
Designing high-quality physical layouts for critical memory blocks (Array, Row/Column Decoders) and periphery circuits for NAND products, ensuring compliance with design rules and enabling tape-out.
Role type
Principal Layout Designer (Senior IC)
Builds
Memory and storage solutions (NAND, DRAM, NOR)
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Cadence VXL, LVS/DRC debugging, Core/Pitch layout fundamentals, Chip Level Integration, Die Size calculations, Floorplanning, ECO/LCO/DFM execution, Tape-out support, Automation/AI tool proficiency
Preferred skills
Mentorship, Innovation in memory generations
Technologies
Cadence VXL
Responsibilities
Implement high-quality layouts under design constraints, debug LVS/DRC issues, create layouts for critical Core/Pitch blocks, coordinate with Design/CAD teams, execute secondary layout tasks, mentor junior members, drive innovation in future memory generations.
Seniority
Principal, hands-on IC with mentorship
