MTS - HIG HBM - ARCHITECTURE
Core
Design and standardize end-to-end IO design quality systems for High Bandwidth Memory (HBM) solutions, ensuring silicon learnings are captured and fed back into future generations.
Role type
Senior IC high-speed IO design architecture engineer
Builds
HBM products for AI and ML applications
Domain
Semiconductor / Memory / High-speed IO
Deliverable
production ML models | product features
Required skills
high-speed clocking design (32Gbps+), IO circuit design (analog and digital), circuit verification and optimization, layout verification, parasitic extraction, off-chip protocols (UCIe, HBM, DDR, PCIe, MIPI), state-of-the-art device characteristics, advanced packaging knowledge (CoWoS, HBM stack, D2D), simulation to silicon correlation, AI-assisted analytics
Preferred skills
circuit debug experience, cross-functional methodology development
Technologies
UCIe, HBM, DDR, PCIe, MIPI, CoWoS, D2D
Responsibilities
Define and standardize IO design quality process from architecture to silicon; correlate silicon measurements and simulation performance for circuit level design analysis; solicit input from Standards, CAD, modeling, and verification groups; leverage AI-assisted analytics to accelerate root cause identification from complex multi-variable silicon data
Seniority
Senior, hands-on IC