Package Silicon Technology Node Development MTS
Core
Define and drive chip-package interaction (CPI) technology strategy and roadmaps to enable advanced silicon node transitions in next-generation memory products.
Role type
Senior IC technical leader (Package Development Engineering)
Builds
Next-generation memory products (DRAM, NAND, NOR) enabling AI, 5G, data center, and mobile applications
Domain
Semiconductor manufacturing, memory technology, chip-package integration
Deliverable
production ML models | product features | infrastructure
Required skills
Chip-package interaction (CPI) strategy, silicon node transition planning, cross-functional technical leadership, risk mitigation in complex design/process landscapes, AI proficiency and AI-based workflow implementation
Preferred skills
Global engineering collaboration, technology readiness assessment, execution excellence in advanced packaging
Technologies
Advanced packaging processes, silicon integration tools, AI-based engineering workflows
Responsibilities
Define CPI technology strategy and roadmaps, operate at the intersection of silicon/package/system-level integration, collaborate with global teams (Fab Process Integration, Product Development, Package Design, Assembly Technology, Quality), manage technology risk and readiness
Seniority
Senior, hands-on IC technical leader