HBM SoC RTL Design Engineer
Core
Design, develop, and integrate next-generation HBM SoC logic die, implementing RTL for SoC-level blocks and subsystems.
Role type
Senior IC RTL Design Engineer (HBM SoC)
Builds
High-performance HBM logic die for memory and storage solutions
Domain
Semiconductor / High-speed memory interfaces
Deliverable
production ML models | product features
Required skills
SystemVerilog/Verilog, SoC integration methodologies, RTL-to-GDS flow, EDA tools (Cadence/Synopsys/Siemens), Python/TCL/Perl/Shell scripting
Preferred skills
HBM/DRAM SoC design, high-speed interfaces, clocking strategies, power management, DFT concepts, hardware emulation platforms, Agentic AI workflows
Technologies
SystemVerilog, Verilog, Python, TCL, Perl, Shell, Cadence, Synopsys, Siemens, Palladium, Veloce, Zebu
Responsibilities
Design and implement RTL for SoC-level blocks and subsystems; Integrate internal and third-party IP; Collaborate with architects to translate specifications into RTL; Participate in SoC-level integration (clocking, reset, power intent); Assist with pre/post-silicon validation and root-cause analysis; Contribute to design documentation and reviews; Collaborate with Product Engineering, Test, and Manufacturing teams
Seniority
Senior, hands-on IC
