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SENIOR ENGINEER FRONT END(FE) CENTRAL PROCESS INTEGRATION ENGINEERING (CPIE) PI

Fab 10A, Singapore💼 Full-time🗓 2026-08-25 → 2026-09-26

Core

Drive packaging product yield, quality improvement, and new product introduction (NPI) for silicon nodes by integrating front-end manufacturing processes and leveraging AI-enabled engineering approaches.

Role type

Senior IC Central Process Integration Engineer (Packaging)

Builds

High-performance DRAM and advanced packaging solutions for data centers, AI, and mobile applications

Domain

Semiconductor manufacturing (DRAM, BEOL integration, advanced packaging)

Deliverable

production ML models | product features

Required skills

Semiconductor device physics, DRAM operations, wafer fabrication process flows, parametric/electrical test, probe yield, BEOL integration, advanced packaging, layout, data analysis, root cause analysis, project management, business process re-engineering

Preferred skills

AI-enabled productivity tools, digital collaboration platforms, strategic thinking, cross-functional collaboration

Technologies

Microsoft Office, Microsoft Copilot, AI-powered tools, data analytics, automation solutions

Responsibilities

Lead PI Loop taskforce to address yield and quality challenges, define strategies for packaging technology qualification ahead of product qualification, promote worldwide synergy through global project management and BKM leveraging, maintain domain knowledge and explore innovation opportunities, drive AI and digital transformation initiatives to enhance engineering efficiency

Seniority

Senior, hands-on IC

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