Principal Digital Design Engineer / Chip Lead
Core
Lead a small senior team to define chip architecture, author RTL, manage timing closure, and drive tape-out for high-speed interface innovations (PHY) enabling AI and advanced computing.
Role type
Principal Digital Design Engineer / Chip Lead
Builds
High-speed interface chips (PHY) for memory and storage solutions
Domain
Semiconductor / Memory and Storage / High-Speed Interfaces
Required skills
SystemVerilog RTL design, Logic synthesis (DC/Genus), Static timing analysis (PrimeTime/Tempus), CDC analysis, IP integration (hard/soft), Tape-out ownership, Architecture specification
Preferred skills
High-speed PHY architectures (SerDes, DDR), I2C management bus, DFT strategy (scan, ATPG), OTP/fuse-based trim
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
Responsibilities
Define top-level chip architecture and partition responsibilities across IP blocks; Author and maintain synthesizable RTL for control blocks and clocking logic; Develop chip-level timing constraints and define clock domain crossing strategy; Drive logic synthesis and guide optimization for PPA targets; Partner with DV staff on assertion-based and coverage-driven verification; Manage IP integration agreements and vendor coordination; Own the tape-out checklist sign-off process; Author architecture and block-level design specifications
Seniority
Principal, technical lead of a small senior team
