Principal Digital Design Engineer / Chip Lead
Core
Lead a small senior team to define chip architecture, integrate hard/soft IP, and drive tape-out of high-speed interface solutions for AI/ML and advanced computing.
Role type
Principal Digital Design Engineer / Chip Lead
Builds
High-speed interface chips (PHY) for memory and storage applications
Domain
Semiconductor / Memory and Storage / High-speed Interfaces
Deliverable
production ML models
Required skills
SystemVerilog RTL design, logic synthesis (DC/Genus), static timing analysis (PrimeTime/Tempus), CDC analysis, IP integration (hard/soft), tape-out ownership, architecture specification
Preferred skills
High-speed PHY architectures (SerDes, DDR), I2C management bus, DFT strategy, OTP/fuse-based trim
Technologies
SystemVerilog, Synopsys Design Compiler, Cadence Genus, PrimeTime, Tempus, VCS, Xcelium, Verdi, DVE, SpyGlass, JasperGold
Responsibilities
Define top-level chip architecture and partition responsibilities across IP blocks; Author and maintain synthesizable RTL for control blocks and clocking logic; Develop chip-level timing constraints and crossing strategies; Drive logic synthesis and guide optimization for PPA targets; Coordinate verification plans and coverage metrics; Manage IP integration agreements and vendor coordination; Own the tape-out checklist sign-off process; Author architecture and interface control documents
Seniority
Principal, technical lead with full ownership
