MTS - DPG Layout
Core
Senior layout engineer responsible for full chip layout design, verification, and team leadership in advanced DRAM and analog memory technologies.
Role type
Senior IC layout engineer (analog/memory)
Builds
Full chip and block-level layouts for DRAM, SRAM, CAM, OTP, and critical analog blocks (PLL, ADC, DAC, LDO, Bandgap, etc.)
Domain
Semiconductor manufacturing, DRAM, Analog VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design, Cadence VLE/VXL, Calibre DRC/LVS, Critical analog block design, Memory layout (DRAM/SRAM/CAM/OTP), Physical layout verification, Scripting and automation, Project management, Team leadership
Preferred skills
Paper publications, AI tool integration for design/verification, Cross-functional collaboration
Technologies
Cadence VLE, Cadence VXL, Calibre
Responsibilities
Drive technical decisions for full chip layout across analog, digital, memory, and ESD domains; Perform LVS/DRC/Antenna verification and quality checks; Establish layout standards and methodologies; Guide junior engineers and manage high-performing teams; Collaborate with global teams (US, Japan, Germany) on project milestones; Validate AI-generated design outputs against specifications and simulations.
Seniority
Senior, hands-on IC with leadership responsibilities