Staff Design and Verification Engineer, Pathfinding
Core
Design and verification of next-generation memory technologies, spanning full-chip functional verification, array architecture definition, and mixed-signal circuit development.
Role type
Staff Design and Verification Engineer (Mixed-Signal/Analog-Digital)
Builds
Advanced memory solutions (DRAM and emerging memories) for the semiconductor industry
Domain
Semiconductor / Memory Technology / Mixed-Signal Circuit Design
Deliverable
production ML models | product features | infrastructure
Required skills
SystemVerilog, Verilog, SPICE simulation, analog-digital circuit composition, custom design flows, UNIX, Cadence environments, semiconductor physics, real-number modeling
Preferred skills
Design-for-test (DFT) methodologies, static timing analysis (STA), timing-accurate Verilog, AI integration in verification workflows
Technologies
SystemVerilog, Verilog, FastSpice, SPICE, Cadence, UNIX
Responsibilities
Perform comprehensive chip-wide functional verification; develop verification plans based on composition specifications; build SystemVerilog testbenches for complete functional coverage; apply SystemVerilog assertions; collaborate with digital design teams for debugging; compose and develop analog-digital circuits
Seniority
Staff, hands-on IC with strategic contribution
