Principal Memory Design Engineer, HBM
Core
Architecting and delivering high-performance DRAM circuit compositions for advanced technology nodes, influencing performance, power, reliability, and time-to-market for next-generation memory products.
Role type
Principal IC design engineer (DRAM memory)
Builds
High-performance DRAM circuits and silicon for next-generation memory products
Domain
Semiconductor / Memory / DRAM
Required skills
DRAM subsystem architecture, CMOS circuit building, VLSI, analog circuits, physical layout, circuit floorplanning, FINESIM, HSPICE, VERILOG
Preferred skills
MS or PhD in Electrical Engineering, industry awareness of memory technology trends, leadership across organizations
Technologies
Cadence Virtuoso, FINESIM, HSPICE, VERILOG
Responsibilities
Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems; Develop and refine floorplans, routing strategies, power delivery networks, sense margins, timings, and die-size tradeoffs; Perform advanced circuit simulations using FINESIM, HSPICE, and VERILOG; Model parasitics, verify power and signal integrity, and support validation, reticle experiments, and tape-out revisions; Drive simulation-to-silicon correlation, identify gaps, and recommend schematic and layout improvements; Lead technical reviews, documentation, and best-practice standardization across design and layout teams; Coordinate and manage layout and build resources, tracking breakthroughs and resolving critical path issues
Seniority
Principal, hands-on IC with technical leadership
