ASIC Design Verification Engineer
Core
Develop advanced verification components for sophisticated System-on-Chip (SoC) designs, ensuring on-time delivery with high quality.
Role type
ASIC Design Verification Engineer
Builds
Simulation environments, verification plans, and testbenches for SoC designs
Domain
Semiconductor / ASIC Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodologies, SystemVerilog, Python, constrained random verification, functional coverage closure, debugging complex functional/integration issues, block/system-level verification planning
Preferred skills
mixed-signal verification, DRAM protocol knowledge (DDR/LPDDR/GDDR), AI/ML techniques for verification automation
Technologies
UVM, SystemVerilog, Python, AI-assisted verification tools
Responsibilities
Develop and maintain UVM-based SystemVerilog verification environments; Build and enhance Python-based testbenches and simulation infrastructure; Execute block and/or system-level verification plans; Debug complex functional and integration issues in close collaboration with design teams; Drive coverage closure and continuously improve verification quality metrics; Explore and adopt AI-assisted techniques to improve verification productivity and debug efficiency
Seniority
Mid-level, hands-on IC
