Principal Engineer, Frontend Organizations Central Team, Dry Etch Process
Core
Lead productivity, yield, and quality improvement engagements for global Dry Etch fleets through plasma process optimization, hardware CIP roadmaps, and defect reduction.
Role type
Principal Engineer, Semiconductor Process & Hardware Optimization
Builds
Dry Etch process windows, hardware CIP roadmaps, and tool efficiency programs for DRAM/NAND manufacturing
Domain
Semiconductor manufacturing (Memory/Storage) - Dry Etch
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Plasma process optimization, Hardware CIP roadmap development, Defect/particle control, Process capability improvement (CD, profile, selectivity), Supplier partnership management, IoT/FDC telemetry setup, Safety & sustainability compliance, Abnormal analysis (FDC, SPC), Tool qualification flows
Preferred skills
Experience with LAM, TEL, AMAT Dry Etch platforms, DRAM/NAND flow expertise, Energy optimization strategies
Technologies
FDC, SPC, RF match networks, Gas delivery systems, Plasma sources, IoT sensors
Responsibilities
Strategize yield and cost improvement via plasma optimization and chemistry qualification; Develop hardware CIP roadmaps for chamber parts and RF networks; Drive defect reduction and chamber-matching across global fleet; Partner with suppliers on tool acceptance criteria and installation requirements; Improve tool efficiency and utilization through benchmarking; Establish process windows and recipe robustness; Enable energy savings and waste reduction solutions.
Seniority
Principal, hands-on IC with strategy & mentorship