Staff Digital Design Engineer, HBM
Core
Designing high-performance digital logic blocks for advanced HBM memory products, translating specifications into robust RTL and optimizing for power, performance, and area.
Role type
Staff Digital Design Engineer (HBM)
Builds
High-bandwidth memory (HBM) digital logic blocks and micro-architecture
Domain
Semiconductor / Memory / Digital Logic Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog/SystemVerilog RTL design, digital logic fundamentals (FSMs, pipelines, datapath), synthesis and static timing analysis (STA), CDC/RDC analysis, low-power design methodologies (CPF/UPF, clock gating), Linux scripting (Python/Perl), micro-architecture definition
Preferred skills
Memory system concepts (DRAM/SRAM, ECC/CRC), AMBA/AXI/APB bus protocols, DFT methodologies, behavioral and timing modeling of macros
Technologies
Verilog, SystemVerilog, Python, Perl, CPF, UPF, Linux
Responsibilities
Drive digital design flow from concept to post-silicon debug; Develop scalable RTL using parameterized design techniques; Define and refine micro-architecture for digital logic blocks; Analyze tradeoffs across area, power, latency, and throughput; Perform CDC/RDC analysis and apply clocking/reset strategies; Support synthesis, STA, and timing constraint creation; Collaborate with verification, DFT, and physical design teams for design closure
Seniority
Senior, hands-on IC
