Staff Engineer, ASIC Physical Design
Core
Lead physical design implementation for processors, controller architectures, and ASICs within the Enterprise SSD Group, focusing on low-power floorplanning, timing closure, and tape-out activities.
Role type
Staff Engineer, ASIC Physical Design
Builds
Enterprise SSD processors, controllers, and ASICs
Domain
Semiconductor / Memory and Storage / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Block-level low-power floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, APR flow development, PPA analysis, Cadence Innovus/Tempus, Caliber physical verification, digital electronics fundamentals, microprocessor architecture
Preferred skills
Advanced process nodes (5nm/3nm), Cadence PnR tools, formal verification
Technologies
Cadence Innovus, Cadence Tempus, Caliber
Responsibilities
Execute block-level STA closure, perform physical verification closure (DRC/LVS/Antenna), resolve IR issues based on feedback, develop APR flows, conduct PPA analysis
Seniority
Senior, hands-on IC