Principal, IO Design Engineering
Core
Design, optimize, and verify high-speed IO and clocking circuits for new DRAM products, pushing speed limits and analyzing impairments like jitter and duty error.
Role type
Principal IO/Clocking Design Engineer
Builds
High-speed memory circuits for DRAM products
Domain
Semiconductor / Analog and Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog and mixed-signal circuit design, high-speed circuit design techniques, device physics, CMOS processing, UNIX, Cadence design environment (simulation, schematic entry, SPF extraction), layout practices for high-speed circuits
Preferred skills
High-speed transmitter/receiver/clocking circuit design, channel modeling, transceiver noise analysis, timing budget analysis, equalization techniques, SI knowledge, mentoring, AI/ML usage, scripting languages (Perl/Python)
Technologies
Cadence, UNIX, Perl, Python
Responsibilities
Innovate, design, optimize, and verify high-speed IO and clocking circuits; Apply high-speed circuit design techniques to evaluate IO data path and clocking path performance; Develop modeling, analysis, and simulation methodologies; Collaborate with Product Engineering and SI teams on silicon performance correlation; Work with process integration and transistor modeling teams on new process nodes
Seniority
Principal, hands-on IC with mentorship