Senior Engineer - Verification Enablement, Test Structure Design and Layout
Core
Enable verification flows for scribe test structure composition, CAD automation, layout development, and reticle creation to support advanced process technology development.
Role type
Senior IC verification and layout engineer
Builds
Scribe test structures, layouts, and reticles for memory and storage products
Domain
Semiconductor manufacturing / IC design
Required skills
IC build flow development, memory design, mixed-signal design, layout engineering, SPICE simulation, EDA tools, automation scripting (SKILL, Python, Perl, Bash, C-Shell)
Preferred skills
Semiconductor device physics, physical verification (LVS, DRC, PEX), Calibre SVRF/TVF rule deck development, machine learning in semiconductor environments, engineering collaboration portals (Confluence, SharePoint), data analytics (Power BI)
Technologies
HSPICE, FineSim, Calibre, SKILL, Python, Perl, Bash, C-Shell, Confluence, SharePoint, Power BI
Responsibilities
Enable and support verification flows for scribe test structure build, layout, and reticle development; Contribute to the development, layout, optimization, and validation of memory, logic, analog, and mixed-signal circuits; Conduct modeling, simulation, parasitic extraction, and post-layout verification; Develop and maintain automation solutions to improve building efficiency, quality, and standardization; Work with diverse groups to aid in process development, manufacturability, and upcoming memory technology advancements
Seniority
Senior, hands-on IC
