Senior Engineer - Verification Enablement, Test Structure Design and Layout
Core
Develop and validate advanced process technologies by enabling verification flows for scribe test structure composition, CAD automation, layout development, and reticle creation.
Role type
Senior IC verification and layout engineer
Builds
Scribe test structures, layouts, and reticles for memory and storage products
Domain
Semiconductor manufacturing / Memory technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
IC build flow development, memory design, mixed-signal design, layout engineering, SPICE simulation, schematic entry, netlist extraction, post-layout verification, automation scripting (SKILL, Python, Perl, Bash, C-Shell)
Preferred skills
Semiconductor device physics, physical verification flows (LVS, DRC, PEX), Calibre SVRF/TVF rule deck development, machine learning methodologies, engineering collaboration portals (Confluence, SharePoint), data analytics tools (Power BI)
Technologies
HSPICE, FineSim, Calibre, Confluence, SharePoint, Microsoft Power BI
Responsibilities
Enable verification flows for scribe test structure build, layout, and reticle development; contribute to development, layout, optimization, and validation of memory, logic, analog, and mixed-signal circuits; conduct modeling, simulation, parasitic extraction, and post-layout verification; develop and maintain automation solutions to improve building efficiency, quality, and standardization; collaborate on process development and manufacturability
Seniority
Senior, hands-on IC