Staff Logic Design Engineer
Core
Design and integrate high-performance IP and RTL logic into Intel's next-generation Client SoC platforms, ensuring design completeness and readiness for downstream integration.
Role type
Staff IC SoC RTL/Logic Design Engineer
Builds
Client SoC platforms and internal IP blocks
Domain
Semiconductor / SoC Design
Required skills
RTL design (Verilog, System Verilog), IP/subsystem architecture, SoC/ASIC design methodology, high-speed bus protocols, front-end tools and flows, AI-assisted engineering workflows, scripting and automation, pre-silicon/post-silicon debug
Preferred skills
Power intent definition, clock domain crossing, formal equivalence verification
Technologies
Verilog, System Verilog, AI tools
Responsibilities
Own internal IP RTL design and development; integrate high-performance IP into SoC platforms; define and deliver new IP features; perform logic and RTL integration including power intent and signal handling; collaborate with verification teams; execute front-end quality checks (static analysis, timing, power convergence)
Seniority
Staff, hands-on IC
