Senior CPU RTL Design Engineer
Core
Design and optimize register transfer level (RTL) logic, simulation, and microarchitecture features for Intel's cutting-edge CPU processors.
Role type
Senior CPU RTL Design Engineer
Builds
CPU IP blocks, functional units, and cell libraries for full-chip integration
Domain
Semiconductor / CPU Architecture
Deliverable
production ML models | product features
Required skills
CPU RTL design, System Verilog, logic design, simulation and debug, low-power design methods, cross-clock domain crossings, scripting (TCL/Perl/Python)
Preferred skills
CPU power management, x86 assembly language, high-speed circuit design, static timing analysis, UPF and lint checks
Technologies
System Verilog, TCL, Perl, Python
Responsibilities
Develop and optimize RTL coding and simulation; define architecture and microarchitecture features; write RTL for power, performance, area, and timing goals; review verification plans; document microarchitectural specifications; collaborate with SoC customers
Seniority
Senior, hands-on IC
