Physical Design for PPA Optimization Engineer
Core
Optimizing Intel's process technology and physical design flows to achieve best-in-class Power, Performance, and Area (PPA) for IPs.
Role type
Physical Design & PPA Optimization Engineer
Builds
Next-generation silicon designs and Intel IPs
Domain
Semiconductor manufacturing and physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical or circuit design, DTCO experiment design, full PnR flow execution, placement, CTS, routing, timing closure, device/cell/block-level analysis, Python/Tcl scripting
Preferred skills
Physical design implementation methodologies, transistor/cell/block-level PPA trade-offs, analysis tool development
Technologies
Python, Tcl
Responsibilities
Define and implement DTCO experiments to evaluate process-physical design interactions; Develop design optimization methodologies across placement, CTS, routing, and timing closure; Run full PnR flows to evaluate technology impacts on PPA metrics; Identify trade-offs and optimization opportunities at device, cell, and block levels.