Senior Logic Design Verification Engineer
Core
Developing verification testbenches, RTL models, and test plans to validate power management controller IP for client and server chipsets.
Role type
Senior IC logic design verification engineer
Builds
Power management controller IP for system boot and power management in client and server chipsets
Domain
Semiconductor / Hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, RTL simulation, BFM, testbench development, debugging, analysis
Preferred skills
UVM Virtual Sequencer, Factory, Formal Property, Assembly language, embedded firmware, RTOS, BIOS, ACPI spec, Python, Perl
Technologies
UVM, System Verilog, RTL simulation tools, Python, Perl, Linux
Responsibilities
Develop verification testbench and building RTL models for verification; Validate and verify functionality of new architectural features by developing testplan, tests content or test tools; Find and implement corrective measures for failing RTL tests; Debug and resolve issues on system platforms using software and RTL simulation tools
Seniority
Senior, hands-on IC
