SoC Compute/Memory Subsystem Architect
Core
Define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms, optimizing system-level performance, scalability, and power efficiency.
Role type
Senior SoC Compute & Memory Architect
Builds
Next-generation IPU/DPU platforms for hyperscale data centers, cloud infrastructure, and AI workloads
Domain
Semiconductor / High-performance networking silicon / SoC architecture
Required skills
SoC/CPU/memory subsystem architecture, Cache hierarchy and coherency modeling, Memory controller design, System-level PPA tradeoff analysis, Multi-generation roadmap planning, Cross-functional technical leadership
Preferred skills
ARM/x86 compute and memory subsystem experience, NUMA systems, IPU/SmartNIC SoC experience, PCIe/CXL memory semantics, Multi-generation architectural ownership
Technologies
DDR, LPDDR, HBM, SMMU/IOMMU, PCIe, CXL, DVFS
Responsibilities
Define multi-level cache hierarchy and coherency models across compute cores and accelerators; Architect system memory subsystems including controllers and scheduling policies; Define SMMU/IOMMU architecture for virtualization-heavy workloads; Optimize data movement across compute, network, and storage subsystems; Lead long-term roadmap for compute and memory evolution; Collaborate with networking, firmware, OS, and validation teams.
Seniority
Senior, hands-on IC
