SoC Compute/Memory Subsystem Architect
Core
Define and drive end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and high-performance memory subsystems for next-generation IPU/DPU platforms.
Role type
Senior SoC Compute & Memory Architect
Builds
High-performance networking silicon (IPU/DPU) for hyperscale data centers, cloud infrastructure, and AI workloads
Domain
Semiconductor / SoC Architecture / Networking
Deliverable
production ML models | product features
Required skills
SoC/CPU/memory subsystem architecture, cache hierarchy design, coherency model definition, memory controller architecture, system-level PPA tradeoff analysis, multi-generation roadmap planning
Preferred skills
ARM/x86 compute and memory subsystem experience, NUMA systems, IPU/SmartNIC/accelerator centric SoCs, PCIe/CXL familiarity, multi-generation architectural ownership
Technologies
DDR, LPDDR, HBM, SMMU/IOMMU, PCIe, CXL, DVFS
Responsibilities
Define multi-level cache hierarchies and coherency models across compute cores and accelerators; Architect memory subsystems including controllers and scheduling policies; Define SMMU/IOMMU architecture for virtualization-heavy workloads; Optimize data movement across compute, network, and storage subsystems; Define power efficiency and scaling strategies; Lead long-term roadmap for compute and memory evolution
Seniority
Senior, hands-on IC
