CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)
Core
Create mask layouts for next-generation SoC/CPU and perform design verification for process rules, reliability, and power integrity.
Role type
Entry-level IC mask layout designer
Builds
CPU and SoC mask layouts for Intel products
Domain
Semiconductor / VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Electrical and Electronic Engineering fundamentals, Unix, VLSI, SoC/CPU Architecture, System Verilog
Preferred skills
None stated
Technologies
None stated
Responsibilities
Create mask layouts meeting project specifications, run design verification tools for PDR, electron migration, voltage drop, and ESD, design and analyze floorplans and power grids, troubleshoot layout and tool flow issues
Seniority
Entry-level, diploma graduate
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