IC Layout Engineering Intern m/f/d
Core
Physical layout and verification of high-performance analog and mixed signal circuits in BiCMOS technologies for energy transformation systems.
Role type
IC Layout Engineering Intern
Builds
Analog and mixed signal integrated circuits using proprietary BiCMOS process technologies
Domain
Semiconductor / Integrated Circuits
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog layout implementation, transistor level layout, layout matching techniques, floor planning, DRC and LVS verification, database structure understanding, revision control, Linux usage, scripting, programming, semiconductor technology basics, IC layout tools (Cadence IC Design Suite)
Preferred skills
Technical project completion, team collaboration, independent task execution, troubleshooting and debugging, German language proficiency
Technologies
Cadence Virtuoso XL, Cadence IC Design Suite, LINUX
Responsibilities
Implement analog layout flow, define block level matching requirements, align block definitions with top level requirements, perform layout verification (DRC, LVS), understand database structure and revision control, learn complete design flow until mask generation
Seniority
Intern