UVM Digital Verification Engineer
Core
Design and simulate circuits at transistor-level, develop verification approaches, and execute verification plans for complex digital and mixed-signal designs in embedded security, cryptography, and signal processing.
Role type
Senior IC digital verification engineer (UVM)
Builds
Production verification environments and testbenches for FPGAs and ASICs
Domain
Semiconductor hardware engineering (ASIC/FPGA)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/UVMF, System Verilog (SVA), constrained-random testing, coverage-driven verification, formal analysis, Python/Perl/Bash scripting, Linux environment, IEEE bus standards (DDR3/4, Amba Axi), RTL design collaboration
Preferred skills
Transistor-level circuit design, physical layout/floor-planning, major industry simulators (Questasim, Xcelium, VCS), mentoring junior engineers
Technologies
UVM, System Verilog, Questasim, Xcelium, VCS, Python, Perl, Bash
Responsibilities
Design and simulate circuits at transistor-level; Develop UVM Agents for proprietary buses; Instantiate VIPs for industry standard buses; Work in block-level/chip-level UVM testbench environment; Work with RTL designers to resolve simulation issues; Perform code reviews and mentor junior engineers
Seniority
Senior, hands-on IC
