Senior UVM Digital Verification Engineer
Core
Senior UVM Digital Verification Engineer developing verification approaches, agents, and testbenches for complex digital and mixed-signal designs in FPGAs and ASICs.
Role type
Senior IC digital verification engineer
Builds
Production verification environments and test plans for embedded security, cryptography, signal/image processing, navigation, and communications
Domain
Defense, space exploration, and biomedical engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/UVMF, System Verilog (SVA), constrained-random testing, coverage-driven verification, formal analysis, Python/Perl/Bash scripting, Linux environment, IEEE bus standards, DDR3/DDR4, Amba Axi protocols
Preferred skills
Master's degree in relevant engineering field, experience with major simulators (Questasim, Xcelium, VCS), experience integrating descriptive modeling tools
Technologies
UVM, System Verilog, SVA, Python, Perl, Bash, Questasim, Xcelium, VCS, DDR3, DDR4, Amba Axi
Responsibilities
Develop verification and test plans, author UVM agents for proprietary buses, instantiate VIPs for industry standard buses, work in block-level/chip-level UVM testbench environments, resolve simulation issues with RTL designers, implement cover groups, perform code reviews, mentor junior engineers
Seniority
Senior, hands-on IC with team leadership
