MTS Digital Verification Engineer
Core
Lead verification strategy and execution for complex digital IPs and SoCs, ensuring signoff quality through methodology, architecture, and cross-functional collaboration.
Role type
Senior IC digital verification engineer (SoC)
Builds
Scalable UVM-based verification environments for complex SoCs and IPs
Domain
Semiconductor design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and signoff closure
Required skills
SystemVerilog, UVM methodology, Assertions (SVA), constrained random verification, regression automation, formal verification, clock/reset domain crossing, Python/Perl/TCL scripting, simulation and debug tools (VCS, Verdi, Spyglass)
Preferred skills
Low-power verification (UPF/CPF)
Responsibilities
Define end-to-end verification strategy for IPs and SoCs; Architect and deploy scalable UVM-based verification environments; Lead block-level, subsystem, and full-chip verification closure; Drive coverage closure (functional, code, assertion); Drive regression automation (CI/CD, infrastructure, dashboards)
Seniority
Senior, hands-on IC
