ASIC Design Verification Engineer
Core
Ensure ASICs in next-generation firewall products meet industry-leading requirements for features, performance, and reliability through comprehensive pre-silicon verification.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Next-generation firewall products
Domain
Cybersecurity / Hardware Design
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, constrained-random methodologies, coverage-driven testing, formal verification, emulation flows, Python automation, C/C++ modeling, debugging complex failures, adversarial test planning, functional coverage modeling, silicon validation bringup
Preferred skills
Networking, cybersecurity domain knowledge, Perl scripting, UNIX shell scripting, regression testing automation, C driver code
Technologies
SystemVerilog, UVM, Python, C, C++, Perl, UNIX shell
Responsibilities
Define verification methodologies and test plans; architect test benches and specify coverage; execute simulation and emulation tests; debug failures and close coverage; create automation tools for triage and metrics; collaborate with software, architecture, and design teams
Seniority
Senior, hands-on IC
