NAND BM IP DV Engineer
Core
Developing test environments, test benches, bus protocol checking, transaction level checking, and constraint random verification for Samsung memory products.
Role type
Design Verification Engineer (Memory)
Builds
Memory IP and System LSI components for Samsung devices
Domain
Semiconductor / Memory / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, SystemVerilog, Verilog, Unix scripting (Shell, TCL, Perl, Python), RTL debugging, verification plan definition, verification metrics setup
Preferred skills
Memory design experience
Technologies
UVM, SystemVerilog, Verilog, Shell, TCL, Perl, Python
Responsibilities
Create and improve existing verification environments, execute tests on RTL, define verification plans and metrics, debug verification issues, collaborate with designers
Seniority
Mid-Senior, hands-on IC
