Senior Digital Verification Engineer
Core
Architect and develop robust verification environments for complex digital IPs, planning full lifecycle verification from planning to coverage closure.
Role type
Senior IC digital verification engineer
Builds
Verification environments and test suites for next-generation memory products (SSD, eMMC/UFS)
Domain
Semiconductor / VLSI / Memory
Required skills
SystemVerilog, UVM, Python scripting, VLSI verification methodology, test planning and coverage closure
Preferred skills
Linux/Unix environments, Cadence tools (Xcelium, vManager, Indago) (via careerplan.io/jobs/D4-005-E2-374-senior-digital-verification-engineer)
Technologies
SystemVerilog, UVM, Python, Xcelium, vManager, Indago
Responsibilities
Plan verification of complex digital IPs by understanding design specifications and collaborating with design engineers; Architect and develop robust verification environments from scratch; Debug tests with design engineers to deliver functionally correct blocks; Execute test plans and achieve coverage closure.
Seniority
Senior, hands-on IC
