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Senior Digital Verification Engineer (CIS)

Tel Aviv-Yafo, Israel💼 Full-time🗓 2026-10-05 → 2026-10-07

Core

Full lifecycle verification of complex digital designs from block to system level for CMOS Image Sensors.

Role type

Senior IC digital verification engineer

Builds

Verification environments and test suites for CIS chips

Required skills

System Verilog, UVM, Perl, Python, digital design verification methodologies, regression testing, coverage closure

Preferred skills

null

Technologies

System Verilog, UVM, Perl, Python

Responsibilities

Plan verification from block to system level, develop verification environments, debug tests with design engineers, collaborate with Design, Algorithm, FW, and Analog teams

Seniority

Senior, hands-on IC