Design-For-Test (DFT) Engineer
Core
Enable effective post-manufacturing chip testing by integrating testability features during the design phase to detect defects and enhance test coverage.
Role type
Design-For-Test (DFT) Engineer
Builds
Production silicon chips with embedded test infrastructure
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features
Required skills
Design for Testability (DFT), scan chain design, Built-In Self-Test (BIST), boundary scan, ATPG setup, scan compression, JTAG/IJTAG, pattern delivery, fault simulation, back-annotated gate level verification, silicon debug, memory and scan diagnostics, Synthesis & Static Timing Analysis, SoC architecture, multi-clock domain design, low power design
Preferred skills
Memory BIST and repair scheme implementation, at-speed test, core-wrapping, IDDQ, Path Delay, Hold Time, RSQ, SSD, IEEE 1149/1500/1687/1838 standards
Technologies
Tessent, VCS, Verdi, DC, PT, Extest
Responsibilities
Perform ATPG timing and no-timing simulation, execute scan compression and insertion techniques, conduct pattern generation for Stuck-at, TDF, and PDF, deliver pattern coverage sign-off, develop test plans and strategies, analyze test results to identify improvements, engage in continuous learning of DFT methodologies
Seniority
Mid-level, hands-on IC
