Design-For-Test (DFT) Engineer
Core
Embed testability features into semiconductor chip designs to enable effective post-manufacturing testing and defect detection.
Role type
Senior IC DFT Engineer
Builds
Semiconductor chips with integrated testability features
Domain
Semiconductor hardware design
Deliverable
production ML models | product features
Required skills
Design for Testability (DFT), scan chain insertion and optimization, Built-In Self-Test (BIST) architectures, boundary scan standards, fault isolation methods, test pattern generation
Preferred skills
None stated
Technologies
None stated
Responsibilities
Lead efforts to integrate testability features into chip designs, coordinate with design and verification teams to optimize test strategies, mentor junior team members in DFT methodologies, drive continuous improvement initiatives to enhance test coverage
Seniority
Senior, hands-on IC with team leadership
