Design-For-Test (DFT) Engineer
Core
Embed testability features into chip designs to facilitate post-manufacturing testing and ensure high-quality silicon.
Role type
Design-For-Test (DFT) Engineer
Builds
Integrated testability features for semiconductor chips
Domain
Semiconductor hardware design
Deliverable
production ML models | product features
Required skills
Design for Testability (DFT), scan chain insertion and optimization, Built-In Self-Test (BIST) architectures, boundary scan implementation, test coverage analysis, fault isolation, silicon validation, post-silicon debug
Preferred skills
NA
Technologies
scan chains, BIST, boundary scan
Responsibilities
Integrate DFT methodologies during the design phase, collaborate with design and verification teams to optimize test efficiency, evaluate and implement new test methodologies, document test design processes and outcomes
Seniority
Mid-level, hands-on IC
