Senior Digital Backend (Place & Route) Layout Engineer
Core
Lead and execute the backend flow of digital ASIC designs from synthesis through to GDSII, optimizing layout for area, power, and performance.
Role type
Senior Digital Backend Layout Engineer (Place & Route)
Builds
Digital ASIC chips for low Earth orbit (LEO) space systems and IoT solutions
Domain
Semiconductor engineering / Space communications
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Place and Route (P&R) flow execution, DRC/LVS compliance, area/power/performance optimization, GDSII generation, frontend-backend integration
Preferred skills
Advanced semiconductor technology experience, strict deadline management
Technologies
GDSII, DRC, LVS
Responsibilities
Execute backend flow from synthesis to GDSII, optimize layout for area/power/performance, ensure DRC/LVS compliance, integrate frontend logic with backend physical design
Seniority
Senior, hands-on IC