Silicon Design Engineer
Core
Develop and enable advanced full-chip physical design methodologies for cutting-edge SoC designs, focusing on Fullchip Floorplan flow development.
Role type
Senior IC silicon design engineer (physical design/CAD methodology)
Builds
Robust and scalable solutions for complex full-chip SoC designs
Domain
Semiconductor / ASIC Physical Design
Required skills
ASIC physical design fundamentals, full-chip physical design, CAD automation, Tcl, Python, Perl, floorplanning, placement, routing, timing analysis, hierarchical design, timing closure, repeater/buffer insertion, feedthrough planning, root-cause analysis, technical leadership, mentoring
Preferred skills
Experience with Cadence Innovus, Synopsys Fusion Compiler/ICC2, long-distance interconnect optimization, cross-functional collaboration
Technologies
Tcl, Python, Perl, Cadence Innovus, Synopsys Fusion Compiler, Synopsys ICC2
Responsibilities
Own and drive major functions' methodology and flow development for large-scale SoC designs; Develop methodologies to identify and optimize repeater and feedthrough requirements; Drive complex technical issues to resolution across timing, interconnect, hierarchy, placement, congestion, and routability; Develop robust and scalable CAD automation; Provide technical leadership, conduct reviews, and mentor junior engineers; Support production projects and drive root-cause analysis
Seniority
Senior, hands-on IC with technical leadership
