PLL Design/ Integration Sr Staff Engineer
Core
Design, integrate, and characterize Phase-Locked Loops (PLLs) for FPGA products across cutting-edge process nodes.
Role type
Sr Staff IC Design Engineer (Analog/Mixed-Signal)
Builds
FPGA products with programmable clocking solutions
Domain
Semiconductor / FPGA / Adaptive Embedded Computing
Required skills
Analog/mixed-signal IC design, PLL architecture (VCO, charge pump, PFD, loop filter), LDO design, Phase Interpolator, High Speed Divider, silicon process knowledge, device physics, post-silicon validation, system-level simulation, Vivado flows
Preferred skills
Fractional-N PLL design, All-Digital PLL (ADPLL), sub-sampling PLL, clock synthesis and recovery (DLL, CDR), digital verification, SystemVerilog modeling
Technologies
Vivado, FPGA, advanced node technologies
Responsibilities
Architect and integrate analog/mixed-signal PLL building blocks into FPGA products, lead integration of PLL topologies to meet power/area/jitter specs, address advanced node challenges like self-heating and VCO linearization, supervise and verify layouts for floor planning and parasitic minimization, conduct PLL bring up and performance characterization in the lab, perform system-level simulations and validation for PLL IP integration
Seniority
Sr Staff, hands-on IC design & mentorship