Silicon Diagnosis DFT Engineer
Core
Conduct post-silicon electrical/physical fault isolation and generate diagnosis patterns to improve debug capabilities for silicon chips.
Role type
Senior IC DFT diagnosis engineer
Builds
Diagnosis patterns, layout databases, and automated diagnosis workflows for silicon validation
Domain
Semiconductor / IC Design / DFT
Required skills
Scan DFT techniques, ATPG, post-silicon fault isolation, electrical/physical fault isolation, layout database management, automation scripting
Preferred skills
C/C++, Verilog, Perl, Python, TCL, ATE, yield analysis, memory design, FPGA design tools, validation tools
Technologies
Xilinx Vivado, VCS, Caliber, Primetime
Responsibilities
Perform post-silicon electrical/physical fault isolation, Work with verification and test team to make diagnosable tests, Build layout databases for diagnosis and cross-probing, Generate scan diagnosis tests for fault isolation, Automate volume diagnosis and data analysis, Develop and apply diagnosis patterns for Soft-Defect-Location or Laser-Voltage-Imaging, Work with design and DFX team for diagnosable designs
