DFT DV Lead
Core
Plan, build, and execute Design-for-Test (DFT) and Design-for-Debug (DFD) verification for AMD's Chiplets to ensure bug-free final designs.
Role type
Senior IC DFT Verification Engineer
Builds
DFT/DFD verification tests and methodologies for next-gen processors and Chiplets
Domain
Semiconductor / Digital Design / Verification
Required skills
DFT Design Verification, SystemVerilog, UVM, Perl scripting, RTL design, JTAG protocols, silicon debug, root cause analysis
Preferred skills
Debug without logs, complex infrastructure adaptation, firmware debugging, mentorship
Technologies
SystemVerilog, UVM, Perl, Python, JTAG, Simulation tools
Responsibilities
Collaborate with architects and design engineers to understand new DFT features; Build directed and random DFT verification tests; Debug test failures and resolve design defects; Analyze and enhance legacy DFT test plans; Write complex Perl scripts to update simulation files; Recreate post-silicon failures in pre-silicon environment; Conduct silicon debug and root cause analysis.
Seniority
Senior, hands-on IC
