PMTS - DFT Architect
Core
Architect, develop, and lead DFT Design and Integration of cutting-edge DFT structures (SCAN, ATPG, MBIST, BSCAN) for next-gen SoC/chiplet and IP, defining DFx architectures from concept to production.
Role type
Senior IC DFT Architect (Silicon Design)
Builds
Next-generation SoC/chiplet and IP debug and observability solutions
Domain
Semiconductor / Silicon Design / DFT
Required skills
DFT methodologies (SCAN, ATPG, MBIST, JTAG), SoC/chiplet architecture, DFX strategy, silicon validation, debug and observability, AI-driven engineering methodologies, automation frameworks, low-power design, clocking and reset architectures
Preferred skills
10+ years in SoC/chiplet/IP design, complex large-scale architecture integration, AI/data-driven techniques for engineering productivity, modern AI-assisted engineering workflows
Technologies
SCAN, ATPG, MBIST, JTAG 1149.x, BSCAN, AI-driven engineering tools
Responsibilities
Develop next-generation SoC/chiplet and IP debug and observability solutions; Partner with architecture teams to define and execute a comprehensive Design-for-Excellence (DFX) strategy; Collaborate with validation and manufacturing teams to establish DFX architectures; Drive cross-functional alignment on DFX requirements and implementation flows; Evaluate and deploy AI-driven methodologies to streamline DFX planning and verification; Define metrics and automation frameworks for DFX solutions
Seniority
Senior, hands-on IC
