STA Engineer - EDA/CAD Flow : Software Development Engineer
Core
Develop and debug Static Timing Analysis (STA) flows and Place & Route algorithms for next-generation processors using Verilog/VHDL.
Role type
Senior IC Digital Design Engineer (STA/EDA Flow)
Builds
High-performance processor designs and EDA verification flows
Domain
Semiconductor / Digital Design / EDA
Required skills
RTL design (Verilog/VHDL), Static Timing Analysis (STA), Timing constraints, Place and Route algorithms, Digital design fundamentals
Preferred skills
Scripting (TCL, Perl, Python), EDA tools and flow, Linux development, Analytical problem-solving
Technologies
Verilog, VHDL, TCL, Perl, Python, Linux, EDA tools
Responsibilities
Create complex digital designs, debug Place & Route (P&R) issues, achieve timing closure, implement STA and timing constraint concepts
Seniority
Mid-level (2-3 years experience)
