Principal ASIC Design Engineer
Core
Provide technical leadership for the development of next-generation IP that enables AMD products across server, data center, client, and embedded markets, optimizing AI-driven data movement for performance, scalability, security, and power efficiency.
Role type
Principal ASIC Design Engineer (Technical Leadership)
Builds
Next-generation IP for AI and high-performance computing products
Domain
Semiconductor / ASIC Design / AI Infrastructure
Deliverable
production ML models
Required skills
RTL design, microarchitecture development, complex IP design, Verilog, SystemVerilog, Python, Perl, Tcl, formal verification, timing closure, post-silicon validation, technical leadership, architectural judgment, mentoring
Preferred skills
Leading ASIC design through tape-outs, high-performance design optimization, AI-enabled engineering tools, cross-functional collaboration
Technologies
Verilog, SystemVerilog, Python, Perl, Tcl
Responsibilities
Provide technical leadership and ownership for critical IOHUB IP development from architecture through tape-out; Partner with architecture teams to evaluate trade-offs and define requirements; Drive design quality to meet functional, timing, area, power, security, and reliability goals; Lead cross-functional collaboration to achieve program milestones; Identify technical risks and develop mitigation strategies; Establish engineering best practices for design quality and scalability; Mentor engineers through architecture reviews and technical decision-making; Drive post-silicon bring-up and root-cause analysis; Communicate technical direction to global engineering leadership.
Seniority
Principal, Technical Leadership & Strategy
