Sr. Manager Physical Design Engineering
Core
Leading end-to-end Physical Design execution for complex SoC and ASIC programs from floorplanning through tapeout signoff.
Role type
Senior Manager, Physical Design Engineering (IC)
Builds
Silicon products (SoC, ASIC)
Domain
Semiconductor / Hardware Design
Required skills
Floorplanning, Place & Route, CTS, Timing Closure, Power Optimization, EMIR, Physical Verification, Design Methodology, Multi-site team management, Technical strategy
Preferred skills
Advanced packaging, 3DIC, AI/Datacenter/Automotive/GPU/CPU SoC experience, Automation/Flow development
Technologies
Advanced process nodes, 3DIC, AI-enabled workflows
Responsibilities
Lead full-chip and block-level Physical Design execution, Drive Floorplanning, PNR, CTS, Timing Closure, Power Optimization, EMIR and Physical Verification signoff, Build and mentor high-performing PD organization, Partner with cross-functional teams (RTL, Architecture, DFT, etc.), Define long-term PD roadmap and capability growth plans
Seniority
Senior, hands-on IC with management responsibilities
