Timing Constraint Development Engineer
Core
Plan and develop timing constraints for IPs, Subsystems, or Full chips, ensuring timing closure through SDC development, verification, and equivalence checking.
Role type
Senior IC Digital Design Engineer (Timing Constraints)
Builds
Next-generation processors, AI chips, and high-performance SoCs
Domain
Semiconductor / Digital IC Design
Required skills
SDC development, Static Timing Analysis (STA), Equivalence Checking, Synthesis, Low Power Design, DFT concepts, Debugging, RTL/Netlist static checks
Preferred skills
Experience with Synopsys FirstHail, Excellicon, or TCM, Top-level/SOC design experience, High-frequency clocking, Scripting and automation, AI interest
Technologies
SDC, Lint, CDC, Synopsys FirstHail, Excellicon, TCM, RTL, Netlist
Responsibilities
Own SDC generation, verification, promotion, and demotion for IPs, SS, and SoCs; Collaborate with design and PNR teams to achieve timing closure; Debug and resolve technical timing issues; Plan and execute tasks per schedule; Guide team members on technical issues
Seniority
Senior, hands-on IC
