Synthesis STA silicon design Engineer
Core
Lead planning and execution of front-end implementation for IP Subsystems, including synthesis, LEC, CLP, and STA timing closure.
Role type
Senior IC silicon design engineer (synthesis STA)
Builds
IP Subsystems and physical partitions for AMD processors
Domain
Semiconductor / Digital IC Design
Required skills
Synthesis, LEC, CLP, Static Timing Analysis (STA), Timing closure, Debugging, Scripting/Automation
Preferred skills
Place and Route (PNR), Top-level/SOC design experience, Complex clocking, Low power design, DFT concepts
Technologies
Synopsys Design Compiler, PrimeTime, Innovus, Verdi, Xcelium
Responsibilities
Execute synthesis and timing closure for IP blocks, Collaborate with PNR and design teams, Plan and schedule implementation tasks, Debug and resolve technical timing issues
Seniority
Senior, hands-on IC
