STA/Constraints Engineer
Core
Developing FullChip constraints and timing closure for System-on-Chip (SOC) and sub-system integration.
Role type
Senior IC STA/Constraints Engineer
Builds
Next-generation processors and AI-enabled chips
Domain
Semiconductor / Digital ASIC Design
Required skills
Static Timing Analysis (STA), SDC development, Clock Domain Crossing (CDC), Timing signoff, Perl/TCL/Shell/Python scripting, Verilog RTL design, Physical Design (PD) tools (Synopsys PT/GCA, ICC2/FC)
Preferred skills
Large digital ASIC project experience, Synthesis experience, Lower power design methodology, Physical implementation experience
Technologies
Synopsys PT, Synopsys GCA, Synopsys ICC2, Synopsys FC, Perl, TCL, Shell, Python, Verilog, SDC
Responsibilities
Own end-to-end delivery of designs from timing constraints and signoff perspective; Work with SOC Architecture team for clocks and statistical timing targets; Ensure clock design requirements are correctly set up in SDC; Understand timing margins (LVF/SSTA/Variations) and collaborate with methodology teams; Collaborate with CAD/EDA vendors to strengthen timing closure methodology; Perform CDC/lint, timing closure, and netlist quality checks; Work on shift-left timing closure.
